Fabrication processes of integrated structures comprising nonvolatile memory cells, that is, arrays of cells arranged in rows and columns, using a double level of polysilicon with a gate dielectric layer and an isolating interpoly dielectric layer between the two levels of polysilicon, are well known and widely used by the industry. Usually, such fabrication processes optionally use a first step of masking and of implantation to define "well" regions having a type of conductivity different than that of the semiconductor substrate, in order to realize n and p channel devices integrated on the same chip. In essence, well known processes, therefore, take advantage of a mask for defining the active areas of different integrated devices (transistors, floating gate memory cells, etc.). Normally the process utilizes a further masking step to realize field isolation implants, that is, to dope the semiconductor in the zones where is subsequently grown a thick oxide layer of definition and isolation of the distinct active areas.
The process may include an anti "punch-through" (APT) implant on all the active areas of the same type of conductivity. This relatively deep implant, that is performed with high energy implantation, also serves to determine a certain threshold, although of a minimum value, of the so-called natural transistors or better said of low threshold transistors that are eventually realized (in order to permit their substantial cut-off).
A relatively "heavy" implant for incrementing the threshold (EPM) is carried out within the so-called matrix area, where the floating gate memory cells are to be realized. Thereafter, over the active areas a thin layer of gate oxide is grown. After depositing and doping a first level polysilicon layer (POLY 1) , a masking and etching step is commonly carried out for a first step of definition of the polysilicon of the first level, so as to define the floating gates of the memory cells. Therefore, over the entire structure is grown and/or deposited a thin dielectric layer of isolation between the two polysilicon levels. Such a thin isolating dielectric layer can be constituted by a multilayer, typically a first oxidation layer, plus a deposited thin layer of silicon nitride, and a third layer produced by thermal oxidation of the nitride layer This interpoly isolating multilayer is commonly called O.N.O.
At this point, it is peculiar to these fabrication processes to include a masking step using a mask commonly referred to as MATRIX mask, to remove the dielectric interpoly layer from all the surface, but the area occupied by the memory cells (MATRIX) . This is followed by the deposition of a layer of doped polysilicon of the second level which, over the areas of the floating gate memory cells, will then be isolated by the dielectric layer from the patterned portions of the polysilicon of first level previously defined. Conversely, outside the area occupied by the matrix memory cells, that is on the areas in which the peripheral transistors and the other devices of the outer circuitry are realized, this second level doped polysilicon layer is directly laid over the existing portions of polysilicon layer of first level.
According to prior art processes, it may also be necessary to carry out a specific masking step in order to accomplish an implant of light voltage shift, known as LVS implant, in the channel areas of standard "enhancement" transistors of the outer circuitry, and while protecting from this LVS implant the channel area of the so-called "natural" or low threshold transistors.
A further masking and etching (POLY 2) step defines the polysilicon of second level. In the matrix area the etching through this (POLY 2) mask stops on the dielectric interpoly layer, while in the outer circuitry area the etching proceeds to define also the underlying polysilicon of the first level. In this way, the channel length of the outer circuitry transistors, including also eventual "natural" or low threshold transistors, is defined in accordance with what has been said regarding the ATP implant. A process of fabrication of this type is described in the Italian Patent Application No. 23737 A/84 and, among others, in the corresponding publication No. GB-2,167,602, both in the name of the present applicant. The pertinent content of these previous publications is herein incorporated by way of reference.